What's New in Version 9.1

Independent X-Axis for Fixed Probes

It is now possible to force graph curves created by a fixed probe to have a separate X-axis, allowing independent zoom. Previously this could only be defined as a manual operation once the curve was plotted.

Available with all versions

LTspice® Compatibility

The schematic editor can now open LTspice® schematics directly; just open the file in the normal way. If all models used are supported by the SIMetrix simulator, a simulation on the schematic can be run with only minimal changes required.

Available with all versions

Testplan Editor

Testplans can now be created and edited using the built-in Testplan Editor. Along with removing the need for third-party spreadsheet or text editor software, the built-in Testplan Editor also provides assitance with various cell inputs. This includes drop-down selection lists and argument entry assistance.

In addition to cell entry assistance, the Testplan Editor also provides real-time error checking. Hover over colored cells to receive further information.

Available with Pro or Elite with VH addon

Testplan Wizards

Dynamically create a DVM tesplan to include only desired Objectives and inputs.

Three Wizards are available:

• DC-DC 1 Input 1 output
• DC-DC 1 Input 2 output
• AC-DC 1 Input 1 output

Available with DVM addon

Improved s and y Parameter Support

The AC table feature that implements s and y parameters has been improved:

1. s-parameter models may now have any number of ports. Previously only 1-port and 2-port devices were supported
2. The schematic support has been improved with a symbol generation feature. A symbol with the required number of connections can automatically be generated given the Touchstone filename extension

Available with all versions

Verilog-A Run-time Debugging Using Microsoft® Visual Studio®

Verilog-A code can now be debugged in real time using Microsoft® Visual Studio®. Visual Studio Community, Professional and Enterprise editions are supported for versions 2012 to 2022.

Instead of debugging the actual Verilog-A code itself, the 'C' code generated by the Verilog-A compiler is opened in the Visual Studio debugger. The debugger allows program flow to be followed as well as being able to view values of variables.

Available with Pro and Elite versions